Logic simulation is the use of a computer program to simulate an operation of a digital circuit i.e. a chip or a combinatorial logic. Thereby two simulation types are applied: Event simulation and cycle simulation.
Event simulation allows the design to contain timing information—the delay needed for a signal to travel from one place to another. During simulation, signal changes are tracked in form of events. A change at a certain time triggers an event after a certain delay. Events are sorted by the time when they will occur, and when all events for a particular time have been handled, the simulated time is advanced to the time of the next scheduled event. How fast an event simulation runs depends on the number of events to be processed, i.e. on the amount of activity in the model.
In cycle simulation it is not possible to specify delays. In cycle simulation a cycle-accurate model is used and every gate is evaluated in every cycle. Cycle simulation therefore runs at a constant speed, regardless of activity in the model.
While event simulation can provide some feedback regarding signal timing, it is not a replacement for static timing analysis. On the other hand, functional verification of logic circuitry using cycle simulation does not include any timing information like signal and gate delays. For this, a separate process is in place using timing assertions. However, often cases occur where timing assertions were wrong and the chip hardware fails due to marginal timing. Disadvantageously timing fails cannot be detected in chip cycle simulation as it does not use any notion of time. To recreate timing fails, event simulators are used, which use either standard delays for gates and wires or use real chip timing information. A drawback of this is that two verification environments need to be set up and maintained, which causes significant overhead. In addition, event simulation on large designs is very slow and sometimes impossible due to memory limitation or runtime constraints.